Previous logic systems, such as Boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. Typically, a combinational logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the circuit, the circuit output is unreliable for a period of time corresponding to the worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is set according to an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
Asynchronous circuits have been proposed that are intended to operate without an independent clock. One asynchronous logic paradigm is disclosed in U.S. Pat. No. 5,305,463 ("NULL Convention Logic"). That paradigm uses logic gates referred to as threshold gates. Within this class, circuits are made with gates having varying numbers of inputs and varying threshold values. Such gates exhibit a switching characteristic in which an output switches from a first state, referred to as NULL, to a second state, referred to as DATA, when a number of inputs in the DATA state equals or exceeds a threshold value. It is desirable for such gates to remain in the DATA state until all gate inputs (or all inputs to a combinational circuit of which the gate is a part) return to NULL. This characteristic of holding an output in a DATA state until all inputs return to NULL is referred to here as "hysteresis."
It is desirable to have a complete family of threshold gates available for rapid prototyping and testing of multi-gate asynchronous circuits, especially threshold gates with hysteresis. Field Programmable Gate Array devices having cells especially-adapted with threshold gate functional blocks are one option, however, a faster and more readily available approach to implementing a wide variety of threshold gates is desirable.